1. Field of the Invention
The present invention relates to a through electrode extending through a silicon substrate of a semiconductor chip, a package base or the like, for accomplishing electrical conduction between the upper and lower surfaces of the silicon substrate. The present invention also relates to a method of manufacturing such through electrode. The present invention also relates to a package base and a semiconductor chip having the through electrode(s).
2. Description of the Related Art
One example of conventional through electrodes is a through electrode made through a plurality of semiconductor chips stacked as a single semiconductor package. This through electrode is fabricated by the following way. A silicon (Si) substrate of a semiconductor wafer has a through electrode formation area. A mask pattern is formed on the substrate other than the through hole formation area. The through electrode forming area is an exposed area and etched by dry etching to form an electrode forming hole having a bottom. The bottom surface and the side surface (hereinafter, referred to as the “inner surface”) of the electrode forming hole are coated with an insulating film, which is made of silicon dioxide (SiO2), by chemical vapor deposition (CVD). Subsequently, a conductive body, which is made of conductive metal, is embedded in the electrode forming hole by plating, and the lower surface of the silicon substrate is polished to expose the conductive body at the bottom of the electrode forming hole. As a result, the through electrode extends from the upper surface to the lower surface of the silicon substrate to accomplish electrical conduction between the upper surface and the lower surface of the silicon substrate. Such through electrode is disclosed in Japanese Patent Application Kokai (Laid Open) No. 10-223833. In particular, see page 6, paragraph 0061 to page 7, paragraph 0082, and FIGS. 4 and 5.
The method of manufacturing the through electrode disclosed in JP 10-223833 may be used as a method of manufacturing a through electrode for accomplishing electrical conduction between the upper and lower surfaces of a package base used in a semiconductor package.
FIG. 13 of the accompanying drawings is a cross-sectional view illustrating a conventional semiconductor package, and FIG. 14 of the accompanying drawings is a plan view of a conventional package base.
Referring to FIGS. 13 and 14, a semiconductor package 101 will be described. A plurality of semiconductor chips 104 are stacked one on another on a package base 105. Each semiconductor chip 104 has through electrodes 102 formed in a chip substrate 103, which is a silicon substrate. The through electrodes 102 of each semiconductor chip 104 are joined with each other by bumps 106 such that the through electrodes 102 of the semiconductor chip 104 are electrically connected with each other. Between the respective semiconductor chips 104 are disposed under-fills 107 to accomplish the insulation between the semiconductor chips 104.
An upper insulating layer 111 is formed on the upper surface 110a of a base substrate 110. The base substrate 110 is a silicon substrate of the package base 105. A rerouting wire 112 made of conductive material is formed on the upper insulating layer 111. The through electrodes 102 of the lowest-layer semiconductor chip 104 are joined with the rerouting wire 112 by the bumps 106 such that the through electrodes 102 are electrically connected to the rerouting wire 112. Through holes 113 are formed in the base substrate 110 from the upper surface 110a thereof to the lower surface 110b thereof. Each through hole 113 has a relatively large inner diameter (for example, Φ 300 μm), and is filled with a conductive body 114 made of copper (Cu) or silver (Ag) so that a through electrode 115 is made. External terminals 116 made of tin-lead alloy (SnPb) or tin-silver alloy (SnAg) are joined to the lower ends of the through electrodes 115. The rerouting wire 112 is electrically connected with the external terminals 116 via the through electrodes 115. The external terminals 116 are connected to wiring terminals of a mounting substrate (not shown). Thus, the stacked semiconductor chips 104 are electrically connected to the mounting substrate via the package base 105.
An insulating layer 120 is formed on the lower surface 110b of the base substrate 110 excluding the external terminals 116. Consequently, the insulation between the base substrate and the mounting substrate is ensured.
FIGS. 15A to 15E of the accompanying drawings is a series of cross-sectional views illustrating a conventional package base manufacturing method.
Referring to FIG. 15A, an electrode forming hole 117 is formed in the upper surface 110a of the base substrate 110 such that the electrode forming hole 117 has a bottom. The electrode forming hole 117 will later become a through hole 113.
As shown in FIGS. 15B and 15B, an insulating film 118 made of silicon dioxide is formed on the inner surface of each electrode forming hole 117 to electrically insulate the conductor body 114 and the base substrate 110 from each other.
A mask pattern 125 (FIG. 15A) is made of a suitable material (e.g., silicon dioxide) to obtain satisfactory etching selectivity (etching depth ratio) to silicon at the time of dry etching.
The conventional package base manufacturing method will be described based on processes PZ1 (FIG. 15A) to PZ5 (FIG. 15E).
At the process PZ1 (FIG. 15A), columnar silicon is sliced to form a silicon substrate, i.e., a base substrate 110. Thereafter, a mask pattern 125 is applied to the upper surface 110a of the base substrate 110 except for the through electrode forming area (in this example, the area where a through hole 113 will be formed and having the same diameter as the through hole 113), and the through electrode forming area is dry-etched to form an electrode forming hole 117 having a bottom.
At the process PZ2 (FIG. 15B), the mask pattern 125 is removed, and an upper face insulating layer 111 and an insulating film 118, both of which are made of silicon dioxide, are formed, by CVD, on the upper surface 110a of the base substrate 110 and on the inner surface of the electrode forming hole 117, respectively.
At the process PZ3 (FIG. 15C), a conductive body 114 is embedded in the electrode forming hole 117 by a plating process, such as electrolytic plating or inelectrolytic plating, such that the inner volume of the electrode forming hole 117 is filled with the conductive body 114.
At the process PZ4 (FIG. 15D), a resist mask is formed on the upper insulating layer 111 by lithography to mask the upper insulating layer 111 except for a rerouting wire forming area where a rerouting wire 112 will be formed. The rerouting wire 112 extends from the top of the conductive body 114 of the electrode forming hole 117 to a bump forming area where a bump 106 connected to a through electrode 115 will be formed. The through electrode is formed by the conductive body 114. Then, the rerouting wire 112 is formed from the top of the through electrode 115 to the bump 106 on the exposed upper insulating layer 111 by the plating. Subsequently, the resist mask is removed, and the bump 106 is formed at the bump forming area of the rerouting wire 112.
At the process PZ5 (FIG. 15E), the lower surface 110b of the base substrate 110 is removed by mechanical grinding or chemical mechanical polishing (CMP) until the conductive body 114 is exposed at the lower surface 110b of the base substrate 110. A lower insulating layer 120 is formed on the polished lower surface 110b of the base substrate 110 by CVD.
Subsequently, an external terminal 116 is joined to the exposed lower end of the conductive body 114. As a result, the conductive body 114, which is embedded in the through hole 113, serves as the through electrode 115 to establish electrical conduction between the upper surface 110a and the lower surface 110b of the base substrate 110.
Thereafter, a wafer is divided into pieces to form a plurality of package bases 105.
In the conventional package base manufacturing method as described above, the through electrode is formed by embedding the conductive body in the electrode forming hole, which is provided to form the through electrode, using a plating process. Filling the electrode forming hole with the conductive body is time consuming, and therefore, the manufacturing efficiency of the through electrode manufacturing process is low.
This problem is especially serious in manufacturing a package base whose electrode forming hole has a relatively large inner diameter because this large hole should be filled with the conductive body.
In order to reduce the time necessary to embed the conductive body in the electrode forming hole, it could be possible that the diameter of the electrode forming hole is decreased to form a slender through hole. In this case, however, the joining strength between the through electrode and the semiconductor chip (or the bump) and between the through electrode and the external terminal of the package base is reduced. Consequently, decreasing the diameter of the electrode forming hole is not preferable.